Modern digital very-large-scale integration (VLSI) circuits commonly operate at supply voltages of around 2.5 volts or below. However, certain integrated circuits (ICs) call for additional on-chip circuits operating at higher voltages. Example circuits are input/output (IO) interface circuits with various off-chip system components such as power management switches, analog input circuits conditioning transducer signals, or output analog drive functions for speakers or other actuators.
One solution to this problem is to use multiple different gate oxide thicknesses and to build both low voltage transistors and high voltage transistors on the same IC chip. This method increases process complexity and cost. An alternative solution is to use lateral asymmetric source and drain MOS transistors having a lightly doped n-type gap between the drain and gate (for n-type devices) to enable use of higher drain to source voltages, such as laterally diffused Metal-Oxide-Semiconductor (LDMOS) or drain-extended MOS (DeMOS) which have drain structures capable of operating at higher voltages as compared to conventional symmetric MOS transistors.
In an LDMOS transistor a lightly doped lateral diffused drain region is constructed between the heavily doped drain contact and the transistor channel region. As the name implies, a lateral current is created between drain and source. A depletion region forms in this lightly doped lateral diffused region resulting in a voltage drop between the drain contact and the transistor gate. With proper design, sufficient voltage may be dropped between the drain contact and the gate dielectric to allow a low gate voltage transistor to be used as a switch for the high voltage.
Some lateral power transistors include “RESURF” regions which is short for reduced surface electric field regions. For purposes of this patent application, the term “RESURF” is understood to refer to a material which reduces an electric field in an adjacent surface semiconductor region. A RESURF region may be for example a buried semiconductor region (or layer) with an opposite conductivity type from the adjacent semiconductor region (or layer). RESURF structures are described in Appels, et. al., “Thin Layer High Voltage Devices” Philips J, Res. 35 1-13, 1980. The RESURF region(s) for lateral power transistors are generally referred to as buried drift regions.
To raise the breakdown voltage of the lateral power transistor a diluted buried drift layer may be used in the drift region at one end of the transistor, which can be formed by a masked implant that enables implanting dilution stripes separated by masked (non-implanted) stripes. One or more high temperature annealing processes follow which results in dopant from the implanted stripes diffusing into the non-implanted stripes which create more heavily doped stripes alternating with less heavily doped stripes.
The DEMOS or LDMOS transistor can have a multi-finger layout with a plurality of source and drain fingers generally interdigitated with one another, or in racetrack layout which is in essence a single finger design with an enclosed source or an enclosed drain. The diluted buried drift layer for diluted buried drift layer designs generally sets the drain-to-source breakdown voltage (BVDSS) for the lateral power transistor, with the racetrack layout generally providing a higher breakdown voltage that is near the ideal (planar) junction breakdown voltage due to less junction curvature as compared to a lower BVDSS for the multi-finger layout having higher curvature at the fingertip regions. Fingertip regions correspond to the curved distal end of the fingers that extend from linear (un-curved) regions of the fingertip Advantages of multi-finger lateral power transistors (e.g., DEMOS or LDMOS transistors) include decreased parasitics effects and the ability to change width (W), length (L), number of fingers, and number of contacts, which helps speed the transistor layout process.